Field of the Invention
The invention relates to a digital signal processing device, particularly for applications as an ADPCM codec.
Particularly for mobile communications, codecs are currently needed that carry out data reduction by half as compared with earlier codecs. One familiar method of data reduction is the ADPCM algorithm, which has already been standardized under CCITT Standard G.721 for a long time. One special feature of that algorithm is that only a very few multiplications and buffer storage operations are needed. Essentially, the only operations that have to be carried out are shift and addition operations and data format conversions, that is conversions from fixed point to floating point representation and vice versa. Modern codecs should also enable convenient sound generation and offer a certain flexibility in implementation of additional functions.
Heretofore either standard signal processors or specially customized logic circuits were used to achieve codec functions. Typical multipurpose signal processor architectures currently being used are optimized for rapid execution of multiplication and buffer storage operations, but are less suitable for the ADPCM algorithm. In particular, format conversions and additional functions such as sound generation, echo compensation and so forth can be implemented only with comparatively great difficulty. Furthermore, the very powerful command set in a multipurpose signal processor is far from being fully exploited. That structure is accordingly not optimal from the standpoint of cost and power consumption. In that respect, structures with specially customized logic circuits are more favorable. However, they only offer very slight flexibility in terms of implementing additional functions.